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| 003 | ISURu | ||
| 005 | 20240721205800.0 | ||
| 008 | 130422t xxu||||| |||| 00| 0 eng d | ||
| 020 | _a9780521187350 | ||
| 041 | _aeng | ||
| 082 |
_a004.22 _bBAE |
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| 100 |
_aBaer, Jean-Loup _9180405 |
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| 245 |
_aMicroprocessor architecture _bfrom simple pipelines to chip multiprocessors |
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| 260 |
_aCambridge _bCambridge University Press _c2010 _g2010 |
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| 300 |
_axiv,367 p. _bill. |
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| 650 | 0 |
_aCACHE HIERARCHY _9180406 |
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| 650 | 0 |
_aCHIP _9180407 |
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| 650 | _aCOMPUTER ARCHITECTURE | ||
| 650 | 0 |
_aELECTRONICS _970813 |
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| 650 | 0 |
_aMEMORY ACCESS _9180408 |
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| 650 | 0 |
_aMICROPROCESSORS _999740 |
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| 650 | 0 |
_aMULTIPROCESSORS _9176779 |
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| 942 |
_2ddc _cL |
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| 999 |
_c130046 _d163433 |
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| 945 |
_dMain Library ADMIN _c26318 |
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